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№1 слайд![Programmable logic and FPGA](/documents_6/f2cfa4aa484b0f57c0da18170ca1fa4e/img0.jpg)
Содержание слайда: Programmable logic and FPGA
CPU Architecture
№2 слайд![Objectives What is a](/documents_6/f2cfa4aa484b0f57c0da18170ca1fa4e/img1.jpg)
Содержание слайда: Objectives
What is a programmable logic
What is an FPGA
Structure
Special functions
Comparison and Usages
Altera Cyclone II 20 FPGA
Design Flow
№3 слайд![Semiconductor Chips](/documents_6/f2cfa4aa484b0f57c0da18170ca1fa4e/img2.jpg)
Содержание слайда: Semiconductor Chips
№4 слайд![Programmable logic An](/documents_6/f2cfa4aa484b0f57c0da18170ca1fa4e/img3.jpg)
Содержание слайда: Programmable logic
An integrated circuit that can be programmed/reprogrammed with a digital logic of a curtain level.
Started at late 70s and constantly growing
Now available of up to approximately 700K Flip-Flops in a single chip.
№5 слайд![Advantages Short Development](/documents_6/f2cfa4aa484b0f57c0da18170ca1fa4e/img4.jpg)
Содержание слайда: Advantages
Short Development time
Reconfigurable
Saves board space
Flexible to changes
No need for ASIC expensive design and production
Fast time to market
Bugs can be fixed easily
Of the shelf solutions are available
№6 слайд![How it Began PLA Programmable](/documents_6/f2cfa4aa484b0f57c0da18170ca1fa4e/img5.jpg)
Содержание слайда: How it Began : PLA
Programmable Logic Array
First programmable device
2-level and-or structure
One time programmable
№7 слайд![SPLD - CPLD Simple](/documents_6/f2cfa4aa484b0f57c0da18170ca1fa4e/img6.jpg)
Содержание слайда: SPLD - CPLD
Simple Programmable logic device
Single AND Level
Flip-Flops and feedbacks
Complex Programmable logic device
Several PLDs Stacked together
№8 слайд![FPGA - Field Programmable](/documents_6/f2cfa4aa484b0f57c0da18170ca1fa4e/img7.jpg)
Содержание слайда: FPGA - Field Programmable Gate Array
№9 слайд![Configuring LUT](/documents_6/f2cfa4aa484b0f57c0da18170ca1fa4e/img8.jpg)
Содержание слайда: Configuring LUT
№10 слайд![Special FPGA functions](/documents_6/f2cfa4aa484b0f57c0da18170ca1fa4e/img9.jpg)
Содержание слайда: Special FPGA functions
Internal SRAM
Embedded Multipliers
and DSP blocks
Embedded logic analyzer
Embedded CPUs
High speed I/O (~10GHz)
DDR/DDRII/DDRIII SDRAM interfaces
PLLs
№11 слайд![Comparison](/documents_6/f2cfa4aa484b0f57c0da18170ca1fa4e/img10.jpg)
Содержание слайда: Comparison
№12 слайд![Usages Digital designs where](/documents_6/f2cfa4aa484b0f57c0da18170ca1fa4e/img11.jpg)
Содержание слайда: Usages
Digital designs where ASIC is not commercial
Reconfigurable systems
Upgradeable systems
ASIC prototyping and emulation
Education
№13 слайд![Manufacturers Xilinx Altera](/documents_6/f2cfa4aa484b0f57c0da18170ca1fa4e/img12.jpg)
Содержание слайда: Manufacturers
Xilinx
Altera
Lattice
Actel
№14 слайд![Cyclone II - , LEs M K RAM](/documents_6/f2cfa4aa484b0f57c0da18170ca1fa4e/img13.jpg)
Содержание слайда: Cyclone II - 20
18,752 LEs
52 M4K RAM blocks
240K total RAM bits
52 9x9 embedded multipliers
4 PLLs
16 Clock networks
315 user I/O pins
SRAM Based volatile configuration
№15 слайд![Cyclone II Internals](/documents_6/f2cfa4aa484b0f57c0da18170ca1fa4e/img14.jpg)
Содержание слайда: Cyclone II Internals
№16 слайд![Cyclone II Logic Array](/documents_6/f2cfa4aa484b0f57c0da18170ca1fa4e/img15.jpg)
Содержание слайда: Cyclone II Logic Array
№17 слайд![Cyclone II Logic Array Block](/documents_6/f2cfa4aa484b0f57c0da18170ca1fa4e/img16.jpg)
Содержание слайда: Cyclone II Logic Array Block (LAB)
16 LEs
Local Interconnect
LE carry chains
Register chains
LAB Control Signals
2 CLK
2 CLK ENA
2 ACLR
1 SCLR
1 SLOAD
№18 слайд![Cyclone II Logic Element LE](/documents_6/f2cfa4aa484b0f57c0da18170ca1fa4e/img17.jpg)
Содержание слайда: Cyclone II Logic Element (LE)
№19 слайд![LE in Normal Mode Suitable](/documents_6/f2cfa4aa484b0f57c0da18170ca1fa4e/img18.jpg)
Содержание слайда: LE in Normal Mode
Suitable for general logic applications and combinational functions.
№20 слайд![LE in Arithmetic Mode Ideal](/documents_6/f2cfa4aa484b0f57c0da18170ca1fa4e/img19.jpg)
Содержание слайда: LE in Arithmetic Mode
Ideal for implementing adders, counters, accumulators, and comparators.
№21 слайд![Cyclone II I O Features In](/documents_6/f2cfa4aa484b0f57c0da18170ca1fa4e/img20.jpg)
Содержание слайда: Cyclone II I/O Features
In/Out/Tri-state
Different Voltages and I/O Standards
Flip-flop option
Pull-up resistors
DDR interface
Series resistors
Bus keeper
Drive strength control
Slew rate control
Single ended/differential
№22 слайд![Cyclone II I O Buffer](/documents_6/f2cfa4aa484b0f57c0da18170ca1fa4e/img21.jpg)
Содержание слайда: Cyclone II I/O Buffer
№23 слайд![Cyclone II Clocking Global](/documents_6/f2cfa4aa484b0f57c0da18170ca1fa4e/img22.jpg)
Содержание слайда: Cyclone II Clocking
16 Global Clocks
4 PLLs
№24 слайд![Cyclone II PLL Outputs Clock](/documents_6/f2cfa4aa484b0f57c0da18170ca1fa4e/img23.jpg)
Содержание слайда: Cyclone II PLL
3 Outputs
Clock Division
Clock Multiplication
Phase shift
№25 слайд![Memory](/documents_6/f2cfa4aa484b0f57c0da18170ca1fa4e/img24.jpg)
Содержание слайда: Memory
№26 слайд![Cyclone II Memory Structure](/documents_6/f2cfa4aa484b0f57c0da18170ca1fa4e/img25.jpg)
Содержание слайда: Cyclone II Memory Structure
№27 слайд![Cyclone II Multipliers x or x](/documents_6/f2cfa4aa484b0f57c0da18170ca1fa4e/img26.jpg)
Содержание слайда: Cyclone II Multipliers
18x18 or 2 9x9 modes
Up to 250MHz Performance
№28 слайд![Delays and maximal frequency](/documents_6/f2cfa4aa484b0f57c0da18170ca1fa4e/img27.jpg)
Содержание слайда: Delays and maximal frequency
Gate delay – Delay of logic element
DFF delay tco (tsu - Very small)
Interconnect delay
№29 слайд![Design flow](/documents_6/f2cfa4aa484b0f57c0da18170ca1fa4e/img28.jpg)
Содержание слайда: Design flow
№30 слайд![Design Rules](/documents_6/f2cfa4aa484b0f57c0da18170ca1fa4e/img29.jpg)
Содержание слайда: Design Rules
№31 слайд![](/documents_6/f2cfa4aa484b0f57c0da18170ca1fa4e/img30.jpg)