Презентация The Verilog Language онлайн
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Слайды и текст к этой презентации:
№2 слайд
![The Verilog Language](/documents_6/f869841a9328a11c2f44e30a4f714aad/img1.jpg)
Содержание слайда: The Verilog Language
Originally a modeling language for a very efficient event-driven digital logic simulator
Later pushed into use as a specification language for logic synthesis
Now, one of the two most commonly-used languages in digital hardware design (VHDL is the other)
Virtually every chip (FPGA, ASIC, etc.) is designed in part using one of these two languages
Combines structural and behavioral modeling styles
№4 слайд
![Behavioral Modeling A much](/documents_6/f869841a9328a11c2f44e30a4f714aad/img3.jpg)
Содержание слайда: Behavioral Modeling
A much easier way to write testbenches
Also good for more abstract models of circuits
Easier to write
Simulates faster
More flexible
Provides sequencing
Verilog succeeded in part because it allowed both the model and the testbench to be described together
№5 слайд
![How Verilog Is Used Virtually](/documents_6/f869841a9328a11c2f44e30a4f714aad/img4.jpg)
Содержание слайда: How Verilog Is Used
Virtually every ASIC is designed using either Verilog or VHDL (a similar language)
Behavioral modeling with some structural elements
“Synthesis subset”
Can be translated using Synopsys’ Design Compiler or others into a netlist
Design written in Verilog
Simulated to death to check functionality
Synthesized (netlist generated)
Static timing analysis to check timing
№6 слайд
![Two Main Components of](/documents_6/f869841a9328a11c2f44e30a4f714aad/img5.jpg)
Содержание слайда: Two Main Components of Verilog
Concurrent, event-triggered processes (behavioral)
Initial and Always blocks
Imperative code that can perform standard data manipulation tasks (assignment, if-then, case)
Processes run until they delay for a period of time or wait for a triggering event
Structure (Plumbing)
Verilog program build from modules with I/O interfaces
Modules may contain instances of other modules
Modules contain local signals, etc.
Module configuration is static and all run concurrently
№7 слайд
![Two Main Data Types Nets](/documents_6/f869841a9328a11c2f44e30a4f714aad/img6.jpg)
Содержание слайда: Two Main Data Types
Nets represent connections between things
Do not hold their value
Take their value from a driver such as a gate or other module
Cannot be assigned in an initial or always block
Regs represent data storage
Behave exactly like memory in a computer
Hold their value until explicitly assigned in an initial or always block
Never connected to something
Can be used to model latches, flip-flops, etc., but do not correspond exactly
Shared variables with all their attendant problems
№8 слайд
![Discrete-event Simulation](/documents_6/f869841a9328a11c2f44e30a4f714aad/img7.jpg)
Содержание слайда: Discrete-event Simulation
Basic idea: only do work when something changes
Centered around an event queue
Contains events labeled with the simulated time at which they are to be executed
Basic simulation paradigm
Execute every event for the current simulated time
Doing this changes system state and may schedule events in the future
When there are no events left at the current time instance, advance simulated time soonest event in the queue
№9 слайд
![Four-valued Data Verilog s](/documents_6/f869841a9328a11c2f44e30a4f714aad/img8.jpg)
Содержание слайда: Four-valued Data
Verilog’s nets and registers hold four-valued data
0, 1
Obvious
Z
Output of an undriven tri-state driver
Models case where nothing is setting a wire’s value
X
Models when the simulator can’t decide the value
Initial state of registers
When a wire is being driven to 0 and 1 simultaneously
Output of a gate with Z inputs
№12 слайд
![Nets and Registers Wires and](/documents_6/f869841a9328a11c2f44e30a4f714aad/img11.jpg)
Содержание слайда: Nets and Registers
Wires and registers can be bits, vectors, and arrays
wire a; // Simple wire
tri [15:0] dbus; // 16-bit tristate bus
tri #(5,4,8) b; // Wire with delay
reg [-1:4] vec; // Six-bit register
trireg (small) q; // Wire stores a small charge
integer imem[0:1023]; // Array of 1024 integers
reg [31:0] dcache[0:63]; // A 32-bit memory
№19 слайд
![A Sequential Primitive](/documents_6/f869841a9328a11c2f44e30a4f714aad/img18.jpg)
Содержание слайда: A Sequential Primitive
Primitive dff( q, clk, data);
output q; reg q;
input clk, data;
table
// clk data q new-q
(01) 0 : ? : 0; // Latch a 0
(01) 1 : ? : 1; // Latch a 1
(0x) 1 : 1 : 1; // Hold when d and q both 1
(0x) 0 : 0 : 0; // Hold when d and q both 0
(?0) ? : ? : -; // Hold when clk falls
? (??) : ? : -; // Hold when clk stable
endtable
endprimitive
№24 слайд
![Procedural Assignment Inside](/documents_6/f869841a9328a11c2f44e30a4f714aad/img23.jpg)
Содержание слайда: Procedural Assignment
Inside an initial or always block:
sum = a + b + cin;
Just like in C: RHS evaluated and assigned to LHS before next statement executes
RHS may contain wires and regs
Two possible sources for data
LHS must be a reg
Primitives or cont. assignment may set wire values
№39 слайд
![FSM from a Single Always](/documents_6/f869841a9328a11c2f44e30a4f714aad/img38.jpg)
Содержание слайда: FSM from a Single Always Block
module FSM(o, a, b);
output o; reg o;
input a, b;
reg [1:0] state;
always @(posedge clk or reset)
if (reset) state <= 2’b00;
else case (state)
2’b00: begin
state <= a ? 2’b00 : 2’b01;
o <= a & b;
end
2’b01: begin state <= 2’b10; o <= 0; end
endcase
№45 слайд
![Simulation Behavior](/documents_6/f869841a9328a11c2f44e30a4f714aad/img44.jpg)
Содержание слайда: Simulation Behavior
Concurrent processes (initial, always) run until they stop at one of the following
#42
Schedule process to resume 42 time units from now
wait(cf & of)
Resume when expression “cf & of” becomes true
@(a or b or y)
Resume when a, b, or y changes
@(posedge clk)
Resume when clk changes from 0 to 1
№50 слайд
![Logic Synthesis Verilog is](/documents_6/f869841a9328a11c2f44e30a4f714aad/img49.jpg)
Содержание слайда: Logic Synthesis
Verilog is used in two ways
Model for discrete-event simulation
Specification for a logic synthesis system
Logic synthesis converts a subset of the Verilog language into an efficient netlist
One of the major breakthroughs in designing logic chips in the last 20 years
Most chips are designed using at least some logic synthesis
№51 слайд
![Logic Synthesis Takes place](/documents_6/f869841a9328a11c2f44e30a4f714aad/img50.jpg)
Содержание слайда: Logic Synthesis
Takes place in two stages:
Translation of Verilog (or VHDL) source to a netlist
Register inference
Optimization of the resulting netlist to improve speed and area
Most critical part of the process
Algorithms very complicated and beyond the scope of this class: Take Prof. Nowick’s class for details
№53 слайд
![What Can Be Translated](/documents_6/f869841a9328a11c2f44e30a4f714aad/img52.jpg)
Содержание слайда: What Can Be Translated
Structural definitions
Everything
Behavioral blocks
Depends on sensitivity list
Only when they have reasonable interpretation as combinational logic, edge, or level-sensitive latches
Blocks sensitive to both edges of the clock, changes on unrelated signals, changing sensitivity lists, etc. cannot be synthesized
User-defined primitives
Primitives defined with truth tables
Some sequential UDPs can’t be translated (not latches or flip-flops)
№54 слайд
![What Isn t Translated Initial](/documents_6/f869841a9328a11c2f44e30a4f714aad/img53.jpg)
Содержание слайда: What Isn’t Translated
Initial blocks
Used to set up initial state or describe finite testbench stimuli
Don’t have obvious hardware component
Delays
May be in the Verilog source, but are simply ignored
A variety of other obscure language features
In general, things heavily dependent on discrete-event simulation semantics
Certain “disable” statements
Pure events
№60 слайд
![Simulation-synthesis](/documents_6/f869841a9328a11c2f44e30a4f714aad/img59.jpg)
Содержание слайда: Simulation-synthesis Mismatches
Many possible sources of conflict
Synthesis ignores delays (e.g., #10), but simulation behavior can be affected by them
Simulator models X explicitly, synthesis doesn’t
Behaviors resulting from shared-variable-like behavior of regs is not synthesized
always @(posedge clk) a = 1;
New value of a may be seen by other @(posedge clk) statements in simulation, never in synthesis
№61 слайд
![Compared to VHDL Verilog and](/documents_6/f869841a9328a11c2f44e30a4f714aad/img60.jpg)
Содержание слайда: Compared to VHDL
Verilog and VHDL are comparable languages
VHDL has a slightly wider scope
System-level modeling
Exposes even more discrete-event machinery
VHDL is better-behaved
Fewer sources of nondeterminism (e.g., no shared variables)
VHDL is harder to simulate quickly
VHDL has fewer built-in facilities for hardware modeling
VHDL is a much more verbose language
Most examples don’t fit on slides
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