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№1 слайд![COMP Computer Architecture](/documents_6/a79723bb4654bfe189b09753f8c6a420/img0.jpg)
Содержание слайда: COMP 206:
Computer Architecture and Implementation
Montek Singh
Mon, Oct 3, 2005
Topic: Instruction-Level Parallelism
(Dynamic Scheduling: Introduction)
№2 слайд![Instruction-Level Parallelism](/documents_6/a79723bb4654bfe189b09753f8c6a420/img1.jpg)
Содержание слайда: Instruction-Level Parallelism
Relevant Book Reading (HP3):
Dynamic Scheduling (in hardware): Appendix A & Chapter 3
Compiler Scheduling (in software): Chapter 4
№3 слайд![Hardware Schemes for ILP Why](/documents_6/a79723bb4654bfe189b09753f8c6a420/img2.jpg)
Содержание слайда: Hardware Schemes for ILP
Why do it in hardware at run time?
Works when can’t know dependences at compile time
Simpler compiler
Code for one machine runs well on another machine
Key idea: Allow instructions behind stall to proceed
DIV.D F0, F2, F4
ADD.D F10, F0, F8
SUB.D F8, F8, F14
Enables out-of-order execution
Implies out-of-order completion
ID stage check for both structural and data dependences
№4 слайд![Dynamic Scheduling](/documents_6/a79723bb4654bfe189b09753f8c6a420/img3.jpg)
Содержание слайда: Dynamic Scheduling
Instructions are issued in order (leftmost I)
Execution can begin out of order (leftmost E)
Execution can terminate out of order (W)
What is I?
№5 слайд![Explanation of I To be able](/documents_6/a79723bb4654bfe189b09753f8c6a420/img4.jpg)
Содержание слайда: Explanation of I
To be able to execute the SUB.D instruction
A function unit must be available
Adder is free in example
There should be no data hazards preventing early execution
None in this example
We must be able to recognize the two previous conditions
Must examine several instructions before deciding on what to execute
I represents the instruction window (or issue window) in which this examination happens
If every instruction starts execution in order, then I is superfluous
Otherwise:
Instruction enter the issue window in order
Several instructions may be in issue window at any instant
Execution can begin out of order
№6 слайд![Out-of-order Execution and](/documents_6/a79723bb4654bfe189b09753f8c6a420/img5.jpg)
Содержание слайда: Out-of-order Execution and Renaming
WAW hazard on register F10: prevents out-of-order execution on machine like CDC 6600
If processor was capable of register renaming:
the WAW hazard would be eliminated
SUB.D could execute early as before
example: IBM 360/91
№7 слайд![Memory Consistency Memory](/documents_6/a79723bb4654bfe189b09753f8c6a420/img6.jpg)
Содержание слайда: Memory Consistency
Memory consistency refers to the order of main memory accesses as compared to the order seen in sequential (unpipelined) execution
Strong memory consistency: All memory accesses are made in strict program order
Weak memory consistency: Memory accesses may be made out of order, provided that no dependences are violated
Weak memory consistency is more desirable
leads to increased performance
In what follows, ignore register hazards
Q: When can two memory accesses be re-ordered?
№8 слайд![Four Possibilities for Load](/documents_6/a79723bb4654bfe189b09753f8c6a420/img7.jpg)
Содержание слайда: Four Possibilities for Load/Store Motion
Load-Load can always be interchanged (if no volatiles)
Load-Store and Store-Store are never interchanged
Store-Load is the only promising program transformation
Load is done earlier than planned, which can only help
Store is done later than planned, which should cause no harm
Two variants of transformation
If load is independent of store, we have load bypassing
If load is dependent on store through memory (e.g., (R1) == (R4)), we have load forwarding
№9 слайд![More on Load Bypassing and](/documents_6/a79723bb4654bfe189b09753f8c6a420/img8.jpg)
Содержание слайда: More on Load Bypassing and Forwarding
Either transformation can be performed at compile time if the memory addresses are known, or at run-time if the necessary hardware capabilities are available
Compiler performs load bypassing in loop unrolling example (next lecture)
In general, if compiler is not sure, it should not do the transformation
Hardware is never “not sure”
№10 слайд![Load Bypassing in Hardware](/documents_6/a79723bb4654bfe189b09753f8c6a420/img9.jpg)
Содержание слайда: Load Bypassing in Hardware
Requires two separate queues for LOADs and STOREs
Every LOAD has to be checked for every STORE waiting in the store queue to determine whether there is a hazard on a memory location
assume that processor knows original program order of all these memory instructions
In general, LOAD has priority over STORE
For the selected LOAD instruction, if there exists a STORE instruction in the store queue such that …
LOAD is behind STORE (in program order), and
their memory addresses are the same
… then the LOAD cannot be sent to memory, and must wait to be executed only after the store is executed
№11 слайд![Example of Load Bypassing](/documents_6/a79723bb4654bfe189b09753f8c6a420/img10.jpg)
Содержание слайда: Example of Load Bypassing
Memory access takes four cycles
Actions at various points in time
End of cycle 1: LQ = [(0)]; SQ = [ ]; execute first load
End of cycle 5: LQ = [(3), (4)]; SQ = [(1)]; execute first load
End of cycle 9: LQ = [(4), (5)]; SQ = [(1), (7)]; execute first load
End of cycle 13: LQ = [(5)]; SQ = [(1), (7)]; load yields to store
We are assuming that no LOADs or STOREs issue between instructions 7 and 22
№12 слайд![History of Dynamic Scheduling](/documents_6/a79723bb4654bfe189b09753f8c6a420/img11.jpg)
Содержание слайда: History of Dynamic Scheduling
First implemented on CDC 6600 and IBM 360/91 in the early 1960s
Fetched and decoded single instr. at a time in program order
Between decoding and execution, instructions stayed in issue window where hazards were detected and resolved
Some hazards resolved before issuing (e.g., availability of FU)
Most data hazards resolved only after issuing
Hazard resolution done with sophisticated hardware scheme
For each instruction in issue window, separately track, monitor, enforce, and eventually resolve all hazards affecting the instruction before it could begin execution
Result: Instructions started execution when they were ready to execute, rather than starting in program order