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    63 слайда
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    1,2,3,4,5,6,7,8,9,10,11
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Слайды и текст к этой презентации:

№1 слайд
Chapter Computer System
Содержание слайда: Chapter 1 Computer System Overview
№2 слайд
Roadmap Basic Elements
Содержание слайда: Roadmap Basic Elements Processor Registers Instruction Execution Interrupts The Memory Hierarchy Cache Memory I/O Communication Techniques
№3 слайд
Operating System Exploits the
Содержание слайда: Operating System Exploits the hardware resources of one or more processors Provides a set of services to system users Manages secondary memory and I/O devices
№4 слайд
A Computer s Basic Elements
Содержание слайда: A Computer’s Basic Elements Processor Main Memory I/O Modules System Bus
№5 слайд
Processor Controls operation,
Содержание слайда: Processor Controls operation, performs data processing Two internal registers Memory address resister (MAR) Memory buffer register (MBR) I/O address register I/O buffer register
№6 слайд
Main Memory Volatile Data is
Содержание слайда: Main Memory Volatile Data is typically lost when power is removed Referred to as real memory or primary memory Consists of a set of locations defined by sequentially numbers addresses Containing either data or instructions
№7 слайд
I O Modules Moves data
Содержание слайда: I/O Modules Moves data between the computer and the external environment such as: Storage (e.g. hard drive) Communications equipment Terminals Specified by an I/O Address Register (I/OAR)
№8 слайд
System Bus Communication
Содержание слайда: System Bus Communication among processors, main memory, and I/O modules
№9 слайд
Top-Level View
Содержание слайда: Top-Level View
№10 слайд
Roadmap Basic Elements
Содержание слайда: Roadmap Basic Elements Processor Registers Instruction Execution Interrupts The Memory Hierarchy Cache Memory I/O Communication Techniques
№11 слайд
Processor Registers Faster
Содержание слайда: Processor Registers Faster and smaller than main memory User-visible registers Enable programmer to minimize main memory references by optimizing register use Control and status registers Used by processor to control operating of the processor Used by privileged OS routines to control the execution of programs
№12 слайд
User-Visible Registers May be
Содержание слайда: User-Visible Registers May be referenced by machine language Available to all programs – application programs and system programs Types of registers typically available are: data, address, condition code registers.
№13 слайд
Data and Address Registers
Содержание слайда: Data and Address Registers Data Often general purpose But some restrictions may apply Address Index Register Segment pointer Stack pointer
№14 слайд
Control and Status Registers
Содержание слайда: Control and Status Registers Program counter (PC) Contains the address of an instruction to be fetched Instruction register (IR) Contains the instruction most recently fetched Program status word (PSW) Contains status information
№15 слайд
Condition codes Usually part
Содержание слайда: Condition codes Usually part of the control register Also called flags Bits set by processor hardware as a result of operations Read only, intended for feedback regarding the results of instruction execution.
№16 слайд
Roadmap Basic Elements
Содержание слайда: Roadmap Basic Elements Processor Registers Instruction Execution Interrupts The Memory Hierarchy Cache Memory I/O Communication Techniques
№17 слайд
Instruction Execution A
Содержание слайда: Instruction Execution A program consists of a set of instructions stored in memory Two steps Processor reads (fetches) instructions from memory Processor executes each instruction
№18 слайд
Basic Instruction Cycle
Содержание слайда: Basic Instruction Cycle
№19 слайд
Instruction Fetch and Execute
Содержание слайда: Instruction Fetch and Execute The processor fetches the instruction from memory Program counter (PC) holds address of the instruction to be fetched next PC is incremented after each fetch
№20 слайд
Instruction Register Fetched
Содержание слайда: Instruction Register Fetched instruction loaded into instruction register Categories Processor-memory, processor-I/O, Data processing, Control
№21 слайд
Characteristics of a
Содержание слайда: Characteristics of a Hypothetical Machine
№22 слайд
Example of Program Execution
Содержание слайда: Example of Program Execution
№23 слайд
Roadmap Basic Elements
Содержание слайда: Roadmap Basic Elements Processor Registers Instruction Execution Interrupts The Memory Hierarchy Cache Memory I/O Communication Techniques
№24 слайд
Interrupts Interrupt the
Содержание слайда: Interrupts Interrupt the normal sequencing of the processor Provided to improve processor utilization Most I/O devices are slower than the processor Processor must pause to wait for device
№25 слайд
Common Classes of Interrupts
Содержание слайда: Common Classes of Interrupts
№26 слайд
Flow of Control without
Содержание слайда: Flow of Control without Interrupts
№27 слайд
Interrupts and the
Содержание слайда: Interrupts and the Instruction Cycle
№28 слайд
Transfer of Control via
Содержание слайда: Transfer of Control via Interrupts
№29 слайд
Instruction Cycle with
Содержание слайда: Instruction Cycle with Interrupts
№30 слайд
Short I O Wait
Содержание слайда: Short I/O Wait
№31 слайд
Long I O wait
Содержание слайда: Long I/O wait
№32 слайд
Simple Interrupt Processing
Содержание слайда: Simple Interrupt Processing
№33 слайд
Changes in Memory and
Содержание слайда: Changes in Memory and Registers for an Interrupt
№34 слайд
Multiple Interrupts Suppose
Содержание слайда: Multiple Interrupts Suppose an interrupt occurs while another interrupt is being processed. E.g. printing data being received via communications line. Two approaches: Disable interrupts during interrupt processing Use a priority scheme.
№35 слайд
Sequential Interrupt
Содержание слайда: Sequential Interrupt Processing
№36 слайд
Nested Interrupt Processing
Содержание слайда: Nested Interrupt Processing
№37 слайд
Example of Nested Interrupts
Содержание слайда: Example of Nested Interrupts
№38 слайд
Multiprogramming Processor
Содержание слайда: Multiprogramming Processor has more than one program to execute The sequence the programs are executed depend on their relative priority and whether they are waiting for I/O After an interrupt handler completes, control may not return to the program that was executing at the time of the interrupt
№39 слайд
Roadmap Basic Elements
Содержание слайда: Roadmap Basic Elements Processor Registers Instruction Execution Interrupts The Memory Hierarchy Cache Memory I/O Communication Techniques
№40 слайд
Memory Hierarchy Major
Содержание слайда: Memory Hierarchy Major constraints in memory Amount Speed Expense Faster access time, greater cost per bit Greater capacity, smaller cost per bit Greater capacity, slower access speed
№41 слайд
The Memory Hierarchy Going
Содержание слайда: The Memory Hierarchy Going down the hierarchy Decreasing cost per bit Increasing capacity Increasing access time Decreasing frequency of access to the memory by the processor
№42 слайд
Secondary Memory Auxiliary
Содержание слайда: Secondary Memory Auxiliary memory External Nonvolatile Used to store program and data files
№43 слайд
Roadmap Basic Elements
Содержание слайда: Roadmap Basic Elements Processor Registers Instruction Execution Interrupts The Memory Hierarchy Cache Memory I/O Communication Techniques
№44 слайд
Cache Memory Invisible to the
Содержание слайда: Cache Memory Invisible to the OS Interacts with other memory management hardware Processor must access memory at least once per instruction cycle Processor speed faster than memory access speed Exploit the principle of locality with a small fast memory
№45 слайд
Principal of Locality More
Содержание слайда: Principal of Locality More details later but in short … Data which is required soon is often close to the current data If data is referenced, then it’s neighbour might be needed soon.
№46 слайд
Cache and Main Memory
Содержание слайда: Cache and Main Memory
№47 слайд
Cache Principles Contains
Содержание слайда: Cache Principles Contains copy of a portion of main memory Processor first checks cache If not found, block of memory read into cache Because of locality of reference, likely future memory references are in that block
№48 слайд
Cache Main-Memory Structure
Содержание слайда: Cache/Main-Memory Structure
№49 слайд
Cache Read Operation
Содержание слайда: Cache Read Operation
№50 слайд
Cache Design Issues Main
Содержание слайда: Cache Design Issues Main categories are: Cache size Block size Mapping function Replacement algorithm Write policy
№51 слайд
Size issues Cache size Small
Содержание слайда: Size issues Cache size Small caches have significant impact on performance Block size The unit of data exchanged between cache and main memory Larger block size means more hits But too large reduces chance of reuse.
№52 слайд
Mapping function Determines
Содержание слайда: Mapping function Determines which cache location the block will occupy Two constraints: When one block read in, another may need replaced Complexity of mapping function increases circuitry costs for searching.
№53 слайд
Replacement Algorithm Chooses
Содержание слайда: Replacement Algorithm Chooses which block to replace when a new block is to be loaded into the cache. Ideally replacing a block that isn’t likely to be needed again Impossible to guarantee Effective strategy is to replace a block that has been used less than others Least Recently Used (LRU)
№54 слайд
Write policy Dictates when
Содержание слайда: Write policy Dictates when the memory write operation takes place Can occur every time the block is updated Can occur when the block is replaced Minimize write operations Leave main memory in an obsolete state
№55 слайд
Roadmap Basic Elements
Содержание слайда: Roadmap Basic Elements Processor Registers Instruction Execution Interrupts The Memory Hierarchy Cache Memory I/O Communication Techniques
№56 слайд
I O Techniques When the
Содержание слайда: I/O Techniques When the processor encounters an instruction relating to I/O, it executes that instruction by issuing a command to the appropriate I/O module. Three techniques are possible for I/O operations: Programmed I/O Interrupt-driven I/O Direct memory access (DMA)
№57 слайд
Programmed I O The I O module
Содержание слайда: Programmed I/O The I/O module performs the requested action then sets the appropriate bits in the I/O status register but takes no further action to alert the processor. As there are no interrupts, the processor must determine when the instruction is complete
№58 слайд
Programmed I O Instruction
Содержание слайда: Programmed I/O Instruction Set Control Used to activate and instruct device Status Tests status conditions Transfer Read/write between process register and device
№59 слайд
Programmed I O Example Data
Содержание слайда: Programmed I/O Example Data read in a word at a time Processor remains in status-checking look while reading
№60 слайд
Interrupt-Driven I O
Содержание слайда: Interrupt-Driven I/O Processor issues an I/O command to a module and then goes on to do some other useful work. The I/O module will then interrupt the processor to request service when it is ready to exchange data with the processor.
№61 слайд
Interrupt- Driven I O
Содержание слайда: Interrupt- Driven I/O Eliminates needless waiting But everything passes through processor.
№62 слайд
Direct Memory Access
Содержание слайда: Direct Memory Access Performed by a separate module on the system When needing to read/write processor issues a command to DMA module with: Whether a read or write is requested The address of the I/O device involved The starting location in memory to read/write The number of words to be read/written
№63 слайд
Direct Memory Access I O
Содержание слайда: Direct Memory Access I/O operation delegated to DMA module Processor only involved when beginning and ending transfer. Much more efficient.
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